Wednesday, 11 March 2015

Details Coming Soon

by Unknown  |  at  07:21


  DCOM



Details Coming Soon . . . . . . . . . . .
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 Please try again latter . . . . . . . . . .  

VLSI Practical no 4

by Unknown  |  in VlSI practical at  07:04
VLSI Practical



Practical no:4

Aim :- Plot the transient characteristics of CMOS NOR gate.

Tools :- Tanner T-spice

Circuit Diagram:-


 
 Figure is shows circuit diagram of CMOS NOR gate

Coding: -
 
           .model nMOS1 nMOS Vth=0.7v Kn=110u gamma=0.4 lambda=0.04 phi=0.7
           .model nMOS2 nMOS Vth=0.7v Kn=110u gamma=0.4 lambda=0.04 phi=0.7
           .model pMOS1 pMOS Vth=0.7v Kn=50u gamma=0.57 lambda=0.05 phi=0.8
           .model pMOS2 pMOS Vth=0.7v Kn=50u gamma=0.57 lambda=0.05 phi=0.8
          

           M1 4 1 5 5 pMOS1 W=3u L=1u

           M2 3 2 4 5 pMOS2 W=3u L=1u

           M3 3 1 0 0 nMOS1 W=1u L=1u

           M4 3 2 0 0 nMOS2 W=1u L=1u



          Vdd 5 0 5v
          vin1 1 0 dc 0 pulse(0 5 0 1n 1n 10n 20n)round=0 ac=0 0
          vin2 2 0 dc 0 pulse(0 5 0 1n 1n 30n 40n)round=0 ac=0 0
          .tran 10n 100n
          .print tran v(1),v(2),v(3)
.         end



Observations:-

Device and node counts:-
                   MOSFETs - 4                               MOSFET geometries - 4      

                   BJTs - 0                                        JFETs - 0      

                   MESFETs - 0                               Diodes - 0      

                   Capacitors - 0                               Resistors - 0      

                   Inductors - 0                                 Mutual inductors - 0      

                   Transmission lines - 0                  Coupled transmission lines - 0      

                   Voltage sources - 3                       Current sources - 0      

                   VCVS - 0                                       VCCS - 0      
                   CCVS - 0                                        CCCS - 0      
                   V-control switch - 0                        I-control switch - 0      
                   Macro devices - 0                          Functional model instances - 0      
                   Subcircuits - 0                                 Subcircuit instances - 0      
                   Independent nodes - 2                    Boundary nodes - 4      
                   Total nodes - 6       


           
       Time:-

                 Parsing                            0.00 seconds

                 Setup                               0.00 seconds

                 DC operating point         0.00 seconds

                 Transient Analysis          0.00 seconds

                 --------------------------------------------------

                 Total                                 0.00 seconds



Waveforms:-
 Input waveform of CMOS NOR circuit which is apply at terminal V(1)

Input waveform of CMOS NOR circuit which is apply at terminal V(2)
 Output waveform of CMOS NOR circuit which is taken from terminal V(3)
Conclusion: -

VLSI Practical no 3

by Unknown  |  in VLSI Practical no 3 at  06:53


 VLSI Practical



Practical no:3

Aim :- Plot the transient characteristics of CMOS NAND gate.

Tools :- Tanner T-spice

Circuit Diagram:-



Figure is shows circuit diagram of CMOS NAND gate



Coding: -
 
           .model nMOS1 nMOS Vth=0.7v Kn=110u gamma=0.4 lambda=0.04 phi=0.7
           .model nMOS2 nMOS Vth=0.7v Kn=110u gamma=0.4 lambda=0.04 phi=0.7
           .model pMOS1 pMOS Vth=0.7v Kn=50u gamma=0.57 lambda=0.05 phi=0.8
           .model pMOS2 pMOS Vth=0.7v Kn=50u gamma=0.57 lambda=0.05 phi=0.8

           M1 4 3 5 5 pMOS1 W=3u L=1u
           M2 4 2 5 5 pMOS2 W=3u L=1u
           M3 4 2 1 0 nMOS1 W=1u L=1u
           M4 1 3 0 0 nMOS2 W=1u L=1u

           Vdd 5 0 5v
           vin1 3 0 dc 0 pulse(0 5 0 1u 1u 20u 30u)round=0 ac=0 0
           vin2 2 0 dc 0 pulse(0 5 0 1u 1u 10u 15u)round=0 ac=0 0
           .tran 1u 100u
           .print tran v(3),v(2),v(4)


Observations:-

Device and node counts:-
                   MOSFETs - 4                               MOSFET geometries - 4      

                   BJTs - 0                                        JFETs - 0      

                   MESFETs - 0                               Diodes - 0      

                   Capacitors - 0                               Resistors - 0      
                   Inductors - 0                                 Mutual inductors - 0      
                   Transmission lines - 0                  Coupled transmission lines - 0      
                   Voltage sources - 3                       Current sources - 0      
                   VCVS - 0                                       VCCS - 0      
                   CCVS - 0                                        CCCS - 0      
                   V-control switch - 0                        I-control switch - 0      
                   Macro devices - 0                          Functional model instances - 0      
                   Subcircuits - 0                                 Subcircuit instances - 0      
                   Independent nodes - 2                    Boundary nodes - 4      
                   Total nodes - 6       


           
       Time:-

                 Parsing                            0.00 seconds

                 Setup                               0.00 seconds

                 DC operating point         0.00 seconds

                 Transient Analysis          0.04 seconds
                 --------------------------------------------------
                 Total                                 0.04 seconds


Waveforms:-
 

Input waveform of CMOS NAND circuit which is apply at terminal V(1)  

Input waveform of CMOS NAND circuit which is apply at terminal V(2) 


Output waveform of CMOS NAND circuit which is taken from terminal V(4)

Conclusion: -

 
 




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